Our Design Methodology

Verien stands for "Verified Engineering", and the check mark in our logo is no accident. At Verien, we simulate at a much higher level than other engineers. This means providing behavioral models for all of the off-the-shelf system elements and using pseudo-code models as the stimulus source for the simulation. In some cases, we've converted diagnostics written in C to VHDL and used these to verify the design.


Pseudo-Code Modeling
Verien has developed intellectual property in the form of templates used to quickly produce bus-functional models of processors and standard busses with stimulus generated by pseudo-code. For example, the following VHDL code could be used to generate the bus cycles to initialize a block of memory:


FOR i IN MEM_START TO MEM_END LOOP
      burst_read(address);
      write(address, data);
END LOOP;


A much more elaborate example can be found here. This is the pseudo-code test for a two chip frame grabber. The simulation testbench for this project consists of the frame grabber board along with four cameras, and PCI target, initiator interfaces, and a PCI bus monitor. In this simulation we acquire from four "cameras" into host memory using scatter/gather DMA and with all data checked at the destination. The cameras are a behavioral model with separate timing parameters for each instance and which generate the selected data pattern (random, incrementing, etc.). The source of stimulus for the project is a behavioral PCI initiator model (a bus functional model) which executes the cycles specified in the above file.


The advantages of pseudo-code models are:

• Stimulus is generated from a high-level language and is more readable.



• The pseudo-code model can access a common project package for address map and bit field definitions. Changes made in the device are instantly reflected in the testbench.



• Pseudo-code models are less prone to errors because of heavy use of symbolic representations of addresses and data.



• The pseudo-code allows the testing of some of the software algorithms on the simulated hardware.



• Switches are provided to enable and disable functions in the testbench (read data checking, type of data pattern generation, etc.). Interrupts and context switches are supported.